1. Field of the Invention
The present invention relates generally to dynamic random access type of semiconductor memory devices and a method of manufacturing thereof, and more particularly, semiconductor memory devices having memory cells structured by a single field effect transistor and a single capacitor, for example, dynamic random access memory (referred to as DRAM hereinafter) and a method of manufacturing the same.
2. Description of the Background Art
DRAM is already well known as shown in, for example, U.S. Pat. No. 4,112,575. FIG. 9 is a block diagram showing one example of an entire structure for a conventional DRAM.
Referring to FIG. 9, the DRAM comprises a memory cell array 1000 including a plurality of memory cells as a memory portion, a row decoder 2000 and a column decoder 3000 connected to address buffers for selecting an address of a memory cell, and an input/output interface portion including a sense amplifier connected to an input/output circuit. The plurality of memory cells of the memory portion are provided in matrix of a plurality of rows and columns. Each memory cell is connected to a corresponding word line connected to the row decoder 2000 and a corresponding bit line connected to the column decoder 3000, thereby forming the memory cell array 1000. A single word line and a single bit line are respectively selected from the row decoder 2000 and the column decoder 3000 by receiving externally applied row address signal and column address signal, thereby selecting a memory cell. Data is written into the selected memory cell or the data stored in the memory cell is read out. Instructions of the data writing/reading are given by a writing/reading control signal applied to a control circuit.
Data is stored in the memory cell array 1000 of N (=n.times.m) bits. Address information of a memory cell to which writing/reading is performed is stored in the row and column address buffers. Memory cells of m bits are coupled to the sense amplifiers through bit lines by a selection of a particular word line (selection of a single word line among n word lines) by means of the row decoder 2000. Then, one of the sense amplifiers is coupled to the input/output circuit by a selection of a particular bit line (selection of a single bit line among m bit lines) by means of the column decoder 3000, so that writing or reading is performed in accordance with instructions of the control circuit.
FIG. 10 is an equivalent circuit showing a memory cell 100 of a conventional DRAM illustrated for explaining writing/reading operation of a memory cell. According to the drawing one memory cell 100 comprises a pair of field effect transistor Q and a capacitor Cs. A gate electrode of the field effect transistor Q is connected to a word line 200, one of source/drain electrodes is connected to one electrode of the capacitor Cs, and the other of the source/drain electrodes is connected to a bit line 300. In data writing, the field effect transistor Q is rendered conductive by an application of a predetermined voltage to the word line 200, so that electric charges applied to the bit line 300 is stored in the capacitor Cs. On the other hand, in data reading, the field effect transistor Q is rendered conductive by the application of a predetermined voltage to the word line 200, so that the electric charges stored in the capacitor Cs is read out through the bit line 300.
FIG. 11 is a partial plan view showing a plane arrangement of a memory cell array portion of a conventional DRAM having a folded bit line structure. FIG. 12 is a sectional view taken along a line XII--XII of FIG. 11.
A structure and an operation of a conventional memory cell will be described in the following with reference to these drawings.
One memory cell is structured by an n channel MOS transistor and a capacitor formed on a major surface of a p type silicon substrate 101. The n channel MOS transistor comprises a gate electrode 103, and n.sup.+ impurity diffusion regions 104a and 104b which are to be source and drain regions. The n.sup.+ impurity diffusion regions 104a and 104b are formed spaced apart from each other on the major surface of the p type silicon substrate 101 so as to define a channel region with a channel surface being a part of the major surface of the silicon substrate 101. The gate electrode 103 is formed on the channel region through a gate oxide film 121. Each of the n.sup.+ impurity diffusion regions 104a and 104b is isolated between the adjacent MOS transistors through a silicon oxide film 102 for isolation. The gate electrode 103 is formed as a word line. A capacitor electrode 106 is formed so as to connect with the n.sup.+ diffusion region 104a through a capacitor oxide film 107 as a dielectric film. A bit line 110 is connected to the n.sup.+ impurity diffusion region 104b through a contact hole 109. An interlayer insulating film 108 is formed between the bit line 110, the word line 103 and the capacitor electrode 106.
Writing operation using a memory cell structured as the foregoing will be described. First, in writing "1" operation, a predetermined voltage is applied beforehand to the n.sup.+ impurity diffusion region 104b through the bit line 110. Then, the n channel MOS transistor is turned on by the application of a predetermined voltage to the gate electrode 103. As a result, electrons in the n.sup.+ impurity diffusion region 104a are drawn out to the n.sup.+ impurity diffusion region 104b side, as indicated by an arrow A of FIG. 12, whereby a potential of the n.sup.+ impurity diffusion region 104a is raised to be the same as that of the n.sup.+ impurity diffusion region 104b. Since the n.sup.+ impurity region 104a is structured so as to oppose to the capacitor electrode 106, electric charges induced by the capacitor electrode 106 are increased as a rise of the potential of the n.sup.+ impurity diffusion region 104a. This state is stored in a memory cell as data of "1".
In writing "0" operation, the potential of the n.sup.+ impurity diffusion region 104b is set to 0V through the bit line 110. The n channel MOS transistor is turned on by an application of a predetermined voltage to the gate electrode 103. At this time, since the potential of the n.sup.+ impurity diffusion region 104a is higher than the potential of the n.sup.+ impurity diffusion region 104b, as indicated by an arrow B in FIG. 12, electrons are injected from the n.sup.+ impurity diffusion region 104b to the n.sup.+ impurity diffusion region 104a, causing the potential of the n.sup.+ impurity diffusion region 104a to fall. As a result, the electric charges induced by the capacitor electrode 106 opposing to the n.sup.+ impurity diffusion region 104a are reduced. This state is stored in a memory cell as data of "0".
In recent years, with the improvement of the manufacturing technique, attempts have been made in highly integrating and miniaturizing a memory cell of a DRAM which is a semiconductor memory device. However, even if a memory cell is miniaturized, a predetermined amount of electric charges should be sufficiently stored as information in each memory cell. Therefore, the surface area occupied by a capacitor portion cannot be smaller above a certain limit, which sets limits to miniaturization of the DRAM. In addition, even if high integration of the memory cell is intended, a power consumed in an entire DRAM is large even though a power consumed in each memory cell is small.